1. Field of the Invention
The present invention relates to trimming an integrated circuit product to better meet specifications, and more particularly to trimming to compensate for process related timing variations.
2. Background Information
Often ICs (integrated circuits) have a number of separate timing circuits built onto one chip. Such timing circuits may include clocks, timing chains, delays and combinations of these and similar timing circuits. As discussed below ICs in practical applications are subject at least to temperature, power supply and process related variations that affect the performance of the circuits on the ICs. When these ICs are being fabricated they are tested under known temperature and power supply conditions so that process related performance differences may be measured, and when out of specification, the chips may be discarded.
One typical IC with separate timing circuits is a serializers/deserializers (SerDes) where a computer system parallel loads a shift register with a data word. The computer system will then trigger, strobe or otherwise start a clock circuit. The clock circuit provides a clock that shifts out the data word one bit at a time. The stream of data bits is sent along with the clock signal to a deserializer. The clock is synchronized to the data signals as they travel and, typically, the clock is used by the deserializer to reliably strobe or load in data, one bit at a time.
Since the clock and the data travel together but in different cables, there may be some skew between the two signals as they are received at a deserializer. To compensate for the skew, usually, the clock is delayed in the deserializer in order to ensure that a clock edge occurs when the data signal is stable. The sequence of delayed clock edges are then used to strobe the data, bit by bit, into a receiving register.
As known to those skilled in the art, the deserializer must be able to reliably receive a data word. Designers will usually send framing bits that surround the data word bits that are sent asynchronously. In this case, by recognizing the framing bits, the beginning and ending of a data word (or byte, etc) are distinguished so that the data word may be reliably retrieved. In the art other techniques are known, including synchronously sending data word bits in a continuous stream with no framing bits but using filler data words.
FIG. 1 illustrates a block diagram of a single IC (integrated circuit) having both a serializer and a deserializer. In this case there are two separate timing circuits, a VCO providing a clock in the serializer and a delay chain in the deserializer. The VCO (voltage controlled oscillator) is started by a strobe signal, STB, that is provided by a computer system that also loaded a parallel data word into a shift register. The VCO clock then shifts out the data word, bit by bit. Coincidently with the data bits, the clock is output on another line. The receiving circuit may use the clock signal to reliably load in the bits.
FIG. 1 includes a deserializer control that accepts a received clock and serial data. The deserializer control delays the clock with respect to the data bit so that the data is stable when the delayed clock loads the data bit by bit into the register. When the full data word is received, the parallel data word is signaled as available to the computing system by the WORD CLK.
As also known to those skilled in that art, performance of electronics on a chip is subject to change due, at least, to variations in operating supply voltage, temperature and fabrication processes. In practice, when a serializer/deserializer IC is fabricated, it is tested. One common test is to run the VCO or other such clock generating circuit and measure its frequency. In this testing, the temperature and the supply voltage are held at known values so that their variations are not operative. However chip to chip process variations will affect the clock frequency.
For example, if the clock frequency is too low due to a “slow” process, the delay in a receiving deserializer may be too long relative to typical process and the timing of the clock and data bit at the receiver may be subject to errors. If the clock frequency is too fast the receiver may again be subject to errors. Process differences may account for as much as a 30% fallout of ICs when tested.
IC designers can specify performance variations due to temperature, supply voltage and process differences under which the IC should reliably operate. Since the designers of an IC can anticipate the performance variations of an IC due to temperature and supply voltage changes, a specification for an acceptable range of VCO frequencies of circuits as they leave the production operation may be developed. For example, the clock frequency may be specified as some center frequency plus or minus an allowable variation. The clock operating at the edges of (and anywhere within) the allowed range will perform reliably over the temperature and supply voltage variations that are published for the IC product.
One limitation in the art is that trimming the VCO clock in a serializer to be within a specified frequency range does not compensate for the same process variations that affect the clock delay in the deserializer.